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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s y s t e m p o w e r p w m c o n t r o l l e r f o r n o t e b o o k c o m p u t e r s w i t h c h a r g e p u m p f e a t u r e s w i d e i n p u t v o l t a g e r a n g e f r o m 6 v t o 2 5 v p r o v i d e 5 i n d e p e n d e n t o u t p u t s w i t h 1 . 5 % a c c u - r a c y o v e r - t e m p e r a t u r e - p w m 1 c o n t r o l l e r w i t h a d j u s t a b l e ( 2 v t o 5 . 5 v ) o u t - p u t - p w m 2 c o n t r o l l e r w i t h a d j u s t a b l e ( 2 v t o 5 . 5 v ) o u t - p u t - 1 0 0 m a l o w d r o p o u t r e g u l a t o r ( l d o 5 ) w i t h f i x e d 5 v o u t p u t - 1 0 0 m a l o w d r o p o u t r e g u l a t o r ( l d o 3 ) w i t h f i x e d 3 . 3 v o u t p u t - 2 7 0 k h z c l o c k s i g n a l f o r 1 5 v c h a r g e p u m p ( u s e d v o u t 1 a s i t s p o w e r s u p p l y ) e x c e l l e n t l i n e / l o a d r e g u l a t i o n s a b o u t 1 . 5 % o v e r - t e m p e r a t u r e r a n g e 1 % , ( 1 . 5 % , 5 0 m a ) 2 . 0 v r e f e r e n c e v o l t a g e o u t p u t b u i l t - i n p o r c o n t r o l s c h e m e i m p l e m e n t e d s e l e c t a b l e f o r c e d - p w m o r a u t o m a t i c p f m / p w m ( w i t h s e l e c t a b l e u l t r a s o n i c o p e r a t i o n ) c o n s t a n t - o n - t i m e c o n t r o l s c h e m e w i t h f r e q u e n c y c o m p e n s a t i o n f o r p w m m o d e s e l e c t a b l e s w i t c h i n g f r e q u e n c y i n p w m m o d e b u i l t - i n d i g i t a l s o f t - s t a r t f o r p w m o u t p u t s a n d s o f t - s t o p f o r p w m o u t p u t s a n d l d o o u t p u t s i n t e g r a t e d b o o t s t r a p f o r w a r d p - c h m o s f e t h i g h e f f i c i e n c y o v e r l i g h t t o f u l l l o a d r a n g e ( p w m s ) b u i l t - i n p o w e r g o o d i n d i c a t o r s ( p w m s ) i n d e p e n d e n t e n a b l e i n p u t s ( p w m s , l d o ) 7 0 % u n d e r - v o l t a g e a n d 1 2 5 % o v e r - v o l t a g e p r o t e c - t i o n s ( p w m ) a d j u s t a b l e c u r r e n t - l i m i t p r o t e c t i o n ( p w m s ) - u s i n g s e n s e l o w - s i d e m o s f e t ? s r d s ( o n ) o v e r - t e m p e r a t u r e p r o t e c t i o n 4 m m x 4 m m t h i n q f n - 2 4 ( t q f n 4 x 4 - 2 4 a ) p a c k a g e l e a d f r e e a n d g r e e n d e v i c e a v a i l a b l e ( r o h s c o m p l i a n t ) g e n e r a l d e s c r i p t i o n s i m p l i f i e d a p p l i c a t i o n c i r c u i t the APW8812 integrates dual step-down, constant-on- time, synchronous pwm controllers (that drives dual n- channel mosfets for each channel) and two low drop- out regulators as well as various protections into a chip. the pwm controllers step down high voltage of a battery to generate low-voltage for nb applications. the output of pwm1 and pwm2 can be adjusted from 2v to 5.5v by setting a resistive voltage-divider from voutx to gnd. the linear regulators provide 5v and 3.3v output for standby power supply. the linear regulators provide up to 100ma output current. when the pwmx output voltage is higher than ldox bypass threshold, the related ldox regulator is shut off and its output is connected to voutx by internal switchover mosfet. it can save power dissipation. the charge pump circuit with 270khz clock driver uses vout1 as its power supply to generate ap- proximately 15v dc voltage. the APW8812 provides excellent transient response and accurate dc output voltage in either pfm or pwm mode. in pulse-frequency mode (pfm), the APW8812 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. the forced-pwm mode works nearly at constant frequency for low-noise requirements. the unique ultrasonic mode maintains the switching frequency above 25khz, which eliminates v out2 l2 q3 pwm2 q4 v out1 v in 6v~28v pwm1 l1 q1 q2 ldo5 ldo3 v ldo 3 v ldo 5 enilim1 enilim2 en ldo charge pump d1 d4 d3 d2 c4 c3 c2 c1 v cp
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 g e n e r a l d e s c r i p t i o n ( c o n t . ) n o t e b o o k a n d s u b - n o t e b o o k c o m p u t e r s p o r t a b l e d e v i c e s d d r 1 , d d r 2 , a n d d d r 3 p o w e r s u p p l i e s 3 - c e l l a n d 4 - c e l l l i + b a t t e r y - p o w e r e d d e v i c e s g r a p h i c c a r d s g a m e c o n s o l e s telecommunications a p p l i c a t i o n s p i n c o n f i g u r a t i o n o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . noise in audio applications. the APW8812 is equipped with accurate sourcing and current-limit, output under-voltage output over-voltage protections, being perfect for nb applications. a 1.7ms (typ.) digital soft-start can reduce the start-up current. a soft-stop function actively discharges the output capaci- tors by the discharge device . the APW8812 has individual enable controls for each pwm channels and ldos. pull- ing both enilim1/2 pin and enldo pin low shuts down the whole chip with low quiescent current close to zero. the APW8812 is available in a tqfn4x4-24a package. = thermal pad (connected to gnd plane for better heat dissipation) bottom view v o u t 1 p o k b o o t 1 u g a t e 1 p h a s e 1 l g a t e 1 vclk ldo 5 vin pgnd skip # en ldo thermal pad tqfn 4 x 4 - 24 a top view 4 3 2 1 6 5 15 16 17 18 13 14 1 0 9 8 7 1 2 1 1 2 1 2 2 2 3 2 4 1 9 2 0 enilim 1 fb 1 ref ton fb 2 enilim 2 v o u t 2 l d o 3 b o o t 2 u g a t e 2 p h a s e 2 l g a t e 2 package code qb : tqfn 4 x 4 - 24 a operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 8812 qb : xxxxx - date code apw 8812 handling code temperature range package code assembly material apw 8812 xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) t h e r m a l c h a r a c t e r i s t i c s ( n o t e 2 ) symbol parameter typical value unit q ja thermal resistance - junction to ambient 52 q jc thermal resistance - junction to case 7 o c/w note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: q ja and q jc are measured with the component mounted on a high effective thermal conductivity test board in free air. the thermal pad of package is soldered directly on the pcb. symbol parameter rating unit v in input power voltage (vin to gnd) - 0.3 ~ 28 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v v boot - gnd boot supply voltage (boot to gnd) - 0.3 ~ 35 v v ug - phase ugate voltage (ugate to phase) <400ns pulse width >400n s pulse width - 5 ~ v boot +0.3 - 0.3 ~ v boot +0.3 v v lg - gnd lgate voltage (lgate to gnd) <400ns pulse width >400ns pulse width - 5 ~ v ldo5 +0.3 - 0.3 ~ v ldo5 +0.3 v v phase phase voltage (phase to gnd) <400ns pulse width >400ns pulse width - 5 ~ 35 - 0.3 ~ 28 v a ll other pins (ldox, fbx, voutx, ldo5, ldo3, ref, vclk, en ldo, enilimx to gnd) - 0.3 ~ 6 v t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature, 10 seconds 260 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s symbol parameter range unit v in pwm1/2 converter input voltage 6 ~ 25 v v out1 pwm1 converter output voltage 2 ~ 5.5 v v out2 pwm2 converter output voltage 2 ~ 5.5 v c in pwm1/2 converter input capacitor (mlcc) 10 ~ m f c ldo ldo output capacitor (mlcc) 2. 2 ~ m f t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s APW8812 symbol parameter test conditions min. typ. max. unit input supply power supply current1, vout1 = vout2 = 0v, skip# = gnd, en ldo = open, enilimx = 5v, v fb1 = v fb2 = 2.05v - 0.55 1.3 ma supply current2, vout1 = 5v, v out2 = 3.3v, skip# = gnd, en ldo = open, enilimx = 5v, v fb1 = v fb2 = 2.05v, p vin +p ldo5 - 5 7 mw standby current, en ldo=open, en pwm=0v - 200 - i vn vin supply current shutdown current, en ldo= 0v, enilimx = 0v - 20 40 m a under - voltage lock out protection (uvlo) rising edge 4.1 4.2 4.3 v ldo5 uvlo threshold hysteresis - 0.1 - v ldo3 uvlo threshold shutdown - 2.5 - v pwm controllers output voltage adjust ra nve vout1, vout2 2 - 5.5 v v fb fbx reference voltage i ref = 0a, t a = - 40 o c to 85 o c 1.98 2.0 2.02 v i fb fbx input current v fbx = 2.0v, t a = 25 o c - 20 - 20 na skip# = ldo5, i out = 0a to 5a - - 1.7 - % skip# = ref, i out = 0a to 5 a - - 1.5 - % pwm 1/2 load regulation skip# = gnd, i out = 0a to 5a - - 0.1 - % pwm1/2 line regulation v in = 6v to 25v - 0.005 - %/v soft - start ramp time enpwm high to v out full regulation - 1.7 - ms t on11 pwm1 on time seting1 ton = gnd, skip# = gnd, v in = 12v, pwm1 = 5v - 2080 - t on12 pwm1 on time seting2 ton = ref, skip# = gnd, v in =12v, pwm1=5v - 1700 - t on13 pwm1 on time seting3 ton = ldo3, skip# = gnd, v in = 12v, pwm1 = 5v - 1390 - t on14 pwm1 on time seting4 ton = ldo5, skip# = gnd, v in =12v, pwm1=5v - 1140 - t on21 pwm2 on time seting1 ton = gnd, skip# = gnd, v in =12v, pwm2 = 3.3v - 1100 - t on22 pwm2 on time seting2 ton = ref, skip# = gnd, v in =12v, pwm2 = 3.3v - 900 - t on23 pwm2 on time seting3 ton = ldo3, skip# = gnd, v in = 12v, pwm2 = 3.3v - 730 - t on24 pwm2 on time seting4 ton = ldo5, skip# = gnd, v in = 12v, pwm2 = 3.3v - 600 - ns ugatex minimum off - time 350 450 550 ns r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t s . t h e s e s p e c i f i c a t i o n s a p p l y o v e r v i n = 1 2 v a n d t a = - 4 0 ~ 8 5 c , u n l e s s o t h e r w i s e s p e c i f i e d . t y p i c a l v a l u e s a r e a t t a = 2 5 c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APW8812 symbol parameter test conditions min. typ. max. unit pwm controllers (cont.) ugatex minimum on - time 80 110 140 ns minimum ultrasonic skip operating frequency 25 37 - khz low drouput linear regulators (ldo5/ldo3) ldo5 output voltage v out1 = gnd, 6v < v in < 25v, 0< i ldo < 100ma 4.8 5.0 5.2 v ldo3 output voltage vout2 = gnd, 6v < v in < 25v, 0< i ldo3 < 100ma 3.2 3.33 3.46 v vout1 regulation voltage rising 4.55 4.7 4.85 v thbyp5 ldo5 bypass threshold for vout1 - to - ldo5 switch on hyst eresis 0.15 0.25 0.3 v vout2 regulation voltage rising 3.05 3.15 3.25 v thbyp3 ldo3 bypass threshold for vout2 - to - ldo3 switch on hysteresis 0.1 0.2 0.25 v voutx - to - ldox switch on resistance voutx to ldox, 10ma - 1.5 3 w ldox current - limit voutx = gn d, ldox = gnd 150 - - ma ldox discharge on resistance - 40 65 w refference ref output voltage i ref = 0a 1.98 2.00 2.02 v ref load regulation i load = 0 to 50 m a - 10 - mv ref sink current ref in regulation 10 - - m a charge pump clock v clkh high l evel voltage i vclk = - 10ma, ldo5 = 5v, t a = 25 o c 4.84 4.92 - v clkl low level voltage i vclk = 10ma, ldo5 = 5v, t a = 25 o c - 0.06 0.12 v f clk clock frequency t a = 25 o c 175 270 325 khz pwm 1/2 protections over - voltage protection threshold v outx rising 12 0 125 130 % over - voltage fault propagation delay delta voltage = 10mv - 1.5 - m s v ilim = 920mv, t a = 25 o c 9.4 10 10.6 m a current - limit current source on the basis of 25 o c - 4500 - ppm/ o c ilimx adjustment range v enilimx - gnd 0.7 - 2 v maximum setting voltage v enilimx = 5v, setting current - limit threshold 205 250 - mv curr ent - limit comparator offset (v enilimx - gnd - v pgnd - phasex ), v enilimx = 920mv - 8 0 8 mv zero - crossing threshold skip# = ref or ldox, v pgnd - phase - 5 0 5 mv under - voltage protection threshold 65 70 75 % under - voltage protection hysteresis - 3 - % under - voltage protection debounce interval 22 32 42 m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t s . t h e s e s p e c i f i c a t i o n s a p p l y o v e r v i n = 1 2 v a n d t a = - 4 0 ~ 8 5 c , u n l e s s o t h e r w i s e s p e c i f i e d . t y p i c a l v a l u e s a r e a t t a = 2 5 c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 6 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APW8812 symbol parameter test conditions min. typ. max. unit pwm 1/2 protections (cont.) under - voltage protection enable blanking time from en signal go high to uvp workable - 2 2.6 ms t j rising - 160 - over - temperature protection threshold hysteresis - 25 - o c power good pok in from lower (pok goes high) 87 90 93 pok in from higher (pok goes low) 120 125 130 pok threshold pok hysteresis - 3 - % pok propagation delay v fbx falling and rising 43 63 85 m s pok enable delay enilmx goes high to pok goes high - 2 - ms pok sink current v pok = 500mv 2.5 7.5 - ma pok leakage current v pok = 5v - 0.1 1 m a logic levels forced pwm mode - - 1.5 v automatic pfg/pwm mode 1.9 - 2.1 v skip# input voltage auto skip with ultrasonic 2.7 - - v 200khz/250khz - - 1.5 v 245khz/305khz 1.9 - 2.1 v 300khz/375khz 2.7 - 3.6 v ton input voltage 365khz/460khz 4.7 - - v enable 450 - - en ilimx input voltage disable - - 400 mv shutdo wn - - 0.4 enable , vclk = off 0.8 - 1.6 en ldo input voltage enable , vclk = on 2.4 - - v v skip# = v ton = 0v or 5v - 1 - 1 m a input leakage current i en ldo 0.5 1 3 m a gate drivers ug pull - up resistance v bootx ? v ugatex = 100mv - 4 8 w ug sink resistance v ugatex ? v phasex = 100mv - 1.5 4 w lg pull - up resistance v ldo5 ? v lgatex = 100mv - 4 8 w lg sink resistance v lgatex ? v pgnd = 100mv - 1.5 4 w ug falling to lg rising - 40 - ns dead - time lg falling to ug rising - 40 - ns vout1/2 discharge on resistance - 40 80 w r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t s . t h e s e s p e c i f i c a t i o n s a p p l y o v e r v i n = 1 2 v a n d t a = - 4 0 ~ 8 5 c , u n l e s s o t h e r w i s e s p e c i f i e d . t y p i c a l v a l u e s a r e a t t a = 2 5 c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 7 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APW8812 symbol parameter test conditions min. typ. max. unit bootstrap switch v f forward voltage v ldo5x ? v bootx - gnd , i f = 10ma - 0.5 0.8 v i r reverse leakage v bootx - gnd = 30v, v phasex = 25v, v ldo5 = 5v - - 0.5 m a r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t s . t h e s e s p e c i f i c a t i o n s a p p l y o v e r v i n = 1 2 v a n d t a = - 4 0 ~ 8 5 c , u n l e s s o t h e r w i s e s p e c i f i e d . t y p i c a l v a l u e s a r e a t t a = 2 5 c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 8 p i n d e s c r i p t i o n pin no. name function 1 enilim1 pwm1 enable and current - limit adjustment. there is an internal 10 m a current source from ldo5 to enilim1 and connected a resistor from enilim1 to gnd to set the current - limit threshold. the pgnd - phase1 current - limit thresh old is 1/10 th the voltage set at enilim1 over a 0.7 to 2v range. the logic current - limit threshold is default to 250mv value if enilim1 is 5v pwm1 is enabled when enilim1=1. when enilim1=0, pwm1 is in shutdown. 2 fb1 output voltage feedback pin (pwm1). it can use a resistive divider from v out1 to gnd to adjust the output from 2 v to 5.5v. 3 ref 2v reference output. bypass to gnd with a 0.1 m f ( minimum ) capacitor. ref can supply external loads for 50 m a (maximum). ref load - regulation error will degrade feedback and output accuracy. 4 ton frequency selection input. connect to ldo5 for 365k hz (pwm1) / 460k hz (pwm2) operation and to ldo3 for 300khz/ 375khz operation . connect to ref for 245khz/305khz operation and to gnd for 200khz/250khz operation . 5 fb2 output voltage feedback pin (pwm 2 ). it can use a resistive divider from v out 2 to gnd to adjust the output from 2 v to 5.5v. 6 enilim2 pwm2 enable an d current - limit adjustment. there is an internal 10 m a current source from ldo5 to enilim2 and connected a resistor from enilim2 to gnd to set the current - limit threshold. the pgnd - phase2 current - limit threshold is 1/10 th the voltage set at enilim2 over a 0.7 to 2v range. the logic current - limit threshold i s default to 250mv value if enilim2 is 5v pwm2 is enabled when enilim2=1. when enilim2=0, pwm2 is in shutdown. 7 vout2 pwm 2 output voltage - sense input. the vout2 pin makes a direct measurement of the pwm2 output voltage. v out 2 is an input to the c onstant - on - time pwm one - time one - shot circuit. 8 ldo3 3.3v linear regulator output. ldo 3 can provide a total of 10 0ma , 3.3v external loads. when ldo 3 is at 3.3 v and pwm2 output voltage is over 3.15 v bypass threshold, the internal ldo will shut down, and ldo 3 outp ut pin connects to vout2 through a 1.5 w switch. bypass to gnd with a minimum of 2.2 m f ceramic capacitor for stability. 9 boot2 supply input for t he ug ate2 gate driver and an internal level - shift circuit. connect to an external capacitor to create a booste d voltage suitable to drive a logic - level n - channel mosfet. 10 ugate2 output of t he h igh - s ide mosfet d river for pwm2 . connect this pin to gate of the high - side mosfet. 11 phase 2 junction p oint of t he h igh - s ide mosfet source, o utput f ilter i nductor and t h e l ow - s ide mosfet drain for pwm2 . connect this pin to the source of the high - side mosfet. phase 2 serves as the lower supply rail for the u gate2 high - side gate driver. phase2 is the current - sense input for the pwm2. 12 lgate2 output of t he l ow - s ide mosfet d river for pwm2 . connect this pin to gate of the low - side mosfet. swings from pgnd to ldo5 . 13 en ldo master enable input. the ldox is enabled when en ldo=1. when enldo=0, the ldo is shutdown. see the table 2 ? power - up control logics. ? 14 skip# pwm1 and 2 controller operation mode control. connect skip# to gnd for forced - pwm mode, to ref for auto pwm/pfm mode and to ldo3 or ldo5 for ultra - sonic mode , 15 pgnd power g round of t he lg ate l ow - s ide mosfet d river s . connect the pin to the s ource of the low - side mosfet s . 16 vin battery voltage input pin. vin powers linear regulators and is also used for the constant - on - time pwm on - time one - shot circuits. connect vin to the battery input and bypass with a 1 m f capacitor for noise interference . 17 ldo5 5v linear r egulator output. ldo 5 can provide a total of 10 0ma , 5v external loads. when ldo 5 is at 5 v and pwm1 output voltage is over 4.7 v bypass threshold, the internal ldo will shut down, and ldo 5 output pin connects to vout1 through a 1.5 w switch. bypass to gnd wit h a minimum of 2.2 m f ceramic capacitor for stability. 18 vclk 270khz clock output for 15v charge pump. 19 lgate1 output of t he l ow - s ide mosfet d river for pwm1 . connect this pin to gate of the low - side mosfet. swings from pgnd to ldo5 . 20 phase 1 junctio n p oint of t he h igh - s ide mosfet source, o utput f ilter i nductor and t he l ow - s ide mosfet drain for pwm1 . connect this pin to the source of the high - side mosfet. phase 1 serves as the lower supply rail for the u gate1 high - side gate driver. phase1 is the curren t - sense input for the pwm1.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 9 p i n d e s c r i p t i o n ( c o n t . ) pin no. name function 21 ugate1 output of t he h igh - s ide mosfet d river for pwm1 . connect this pin to gate of the high - side mosfet. 22 boot1 supply input for t he ug ate1 gate driver and an internal level - shift circuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 23 pok power - g ood o utput p in of both pwm s . (logic and) p ok is an open - drain output used to i ndicate the status of the pwmx output voltage. connect the pok in to +5v through a pull - h igh resistor. 24 vout1 pwm 1 output voltage - sense input. the vout1 pin makes a direct measurement of the pwm1 output voltage. v out 1 is an input to the c onstant - on - time pwm one - time one - shot circuit. thermal pad gnd signal ground for the ic.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 0 b l o c k d i a g r a m ldo uvlo ton smps2 pwm2 controller en enable power on sequence clear fault latch ton generator ov2 uv2 70% v f b2 125% v f b2 pok2 fault latch logic ov1 uv1 70% v f b1 125% v f b1 pwm frequency control soft- stop vout2 soft- stop vout1 en ldo or enilim2 phase1 phase2 ref enable ldo5 ldo5 ldo3 v thbyp 3 ldo5 v thbyp 5 a daptive dead-time diode emulation pwm/pfm transition a daptive dead-time diode emulation pwm/pfm transition smps1 pwm2 controller vout2 vout1 skip# skip# en ldo or enilim1 90% v fb2 pok1 90% v f b1 enilim2 pok fb2 enilim1 boot2 ugate2 phase2 lgate2 ldo3 vout2 skip# ref fb1 boot1 ugate1 phase1 lgate1 vin ldo5 vout1 en ldo gnd vclk pgnd soft- start charge pump oscillator current- limit controller ref thermal shutdown
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 1 t y p i c a l a p p l i c a t i o n c i r c u i t c ldo3 4.7 m f v in : 6 v to 25v boot2 ugate2 phase2 lgate2 fb2 enilim2 vout2 c boot2 0.22 m f c out2 330 m f/6.3vx2 4m w l out2 2.2 m h c in2 10 m f q3 apm4810 v out2 3.3 v/ 11 a ref r boot2 0 boot1 ugate1 phase1 lgate1 fb1 vout1 c boot1 0.1 m f c out1 330 m f/6.3v 9m w l out1 4.7 m h c in1 10 m f q1 apm4810 v out1 5v/ 7 a r boot1 0 pgnd pgnd ldo5 q2 apm4810 q4 apm4810 ldo3 vin en ldo enilim1 skip# gnd r ilim2 200k c ref 0.1 m f c ldo5 4.7 m f on off ton pok gnd r pok 200k r ilim1 200k r top1 30k r top2 13k r gnd2 20k r gnd1 20k vclk v cp 15 v c cp1 100n f c cp2 100n f c cp3 100n f c cp4 1 m f d1 d2 d3 d4
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 2 f u n c t i o n d e s c r i p t i o n c o n s t a n t - o n - t i m e p w m c o n t r o l l e r w i t h i n p u t f e e d - f o r - w a r d the constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time controlled by the on-time generator is determined solely by a one- shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time gen- erator block. the switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstanding than a conventional constant-on- time controller, which has large switching frequency varia- tion over input voltage, output current and temperature. both in pfm and pwm, the on-time generator, which senses input voltage on vin pin, provides very fast on- time response to input line transients. another one-shot sets a minimum off-time (typ.: 300ns). the on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the current- limit threshold, and the minimum off-time one-shot has timed out. forced-pwm mode connect skip# to gnd for normal forced-pwm operation. the forced-pwm mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current zero crossing. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while ugate maintains a duty factor of v out /v in . the benefit of forced- pwm mode is to keep the switching frequency fairly constant. the forced-pwm mode is the most useful for reducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- namic output voltage adjustment. pulse-frequency modulation (pfm) mode connect skip# to ref for normal pfm operation. in pfm mode, an automatic switchover to pulse-frequency modu- lation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on- time of pfm is given by: ultrasonic mode connecting skip# to ldo3 or ldo5 for ultrasonic mode. the ultrasonic mode activates a unique pfm mode with a minimum switching frequency of 37khz. the minimum frequency 37khz of ultrasonic mode eliminates audio- frequency interference in light load condition. it will transit to unique pfm mode when output loading makes the frequency bigger than ultrasonic frequency. in ultrasonic mode, the controller automatically transits to fixed-fre- quency pwm operation when the load reaches the same critical conduction point (i load(pfm to pwm) ). when the controller detects that no switching has oc- curred within about 27 m s (typ.), an ultrasonic pulse will occurre. the ultrasonic controller turns on the low-side mosfet first to reduce the output voltage. after feedback voltage drops below the internal reference voltage, the in out sw pfm - on v v f 1 t = where f sw is the nominal switching frequency of the con- verter in pwm mode. similarly, the on-time of ultrasonic mode is the same with pfm mode. the description of ultrasonic mode will be illustrated later. the load current at handoff from pfm to pwm mode is given by: pfm on out in pwm) to load(pfm t l v v 2 1 i - - = in out sw out in v v f 1 l 2 v v - =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 3 reference voltages and linear regulator (ref and ldo3/5) the 2v reference, ref, is accurate to 1% over- temperature. bypass to gnd with a 0.1 m f (minimum) capacitor. ref can source up to 50 m a for external loads. however, avoid loading ref if extremely accurate speci- fications for both the main output voltages and ref are essential. in addition, ref voltage must be bigger than its rising enable threshold, and then the ldo output starts to rise up. the ldo3 and ldo5 regulators can supply up to 100ma for external loads. bypass to gnd with a minimum of 2.2 m f ceramic capacitor for stability. when enldo is enabled, the v ldo3 is fixed 3.33v and the v ldo5 is fixed 5v in standby mode. when pwmx output voltage is over whose bypass threshold(pwm1 is 4.7v and pwm2 is 3.15v), the switchover between the internal ldox and voutx is workable. these actions change the current path to power the loads from the pwmx regulateon voltage, rather than from the internal linear regulator. f u n c t i o n d e s c r i p t i o n ( c o n t . ) ultrasonic mode (cont.) a power-on-reset (por) function is designed to prevent wrong logic controls. the por function continually moni- tors the supply voltage on the ldo5 pins. ldo5 por circuitry inhibits wrong switching. when the rising v ldo5 voltage reaches the rising por threshold (4.2v typ.), the output voltages begin to ramp up. when the ldo5 volt- age is lower than 4.1v(typ.) or ldo3 voltage is lower than 2.5v(typ.), both switch power supplies are shut off. this is non-latch protection. ldo5 por threshold could reset the under-voltage, over-voltage. power-on-reset t h e a p w 8 8 1 2 i n t e g r a t e s d i g i t a l s o f t - s t a r t c i r c u i t t o r a m p u p t h e p w m x o u t p u t v o l t a g e o f t h e c o n v e r t e r t o t h e p r o - g r a m m e d r e g u l a t i o n s e t p o i n t a t a p r e d i c t a b l e s l e w r a t e . t h e s l e w r a t e o f p w m x o u t p u t v o l t a g e i s i n t e r n a l l y c o n - t r o l l e d t o l i m i t t h e i n r u s h c u r r e n t t h r o u g h t h e o u t p u t c a - p a c i t o r s d u r i n g s o f t - s t a r t p r o c e s s . w h e n t h e e n i l i m x p i n i s p u l l e d a b o v e t h e r i s i n g t h r e s h o l d v o l t a g e , t h e r e l a t e d p w m i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p u p t h e o u t p u t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l i s 1 . 7 m s ( t y p . ) a n d i n d e - p e n d e n t o f t h e u g a t e s w i t c h i n g f r e q u e n c y . d i g i t a l s o f t - s t a r t the APW8812 has two independent enable controls for pwm and ldo. when the enldo pin is higher than 0.8v, the ref, ldo3 and ldo5 are enabled to standby mode. it means that the pwm1 and pwm2 are ready to enable at this mode. when the enpwm pin is high (enilimx=1) at standby mode, the pwmx initiates a soft-start process to ramp up the output voltage. the pwm1 and pwm2 are controlled individually by enilim1 and enilim2. when enldo, enilim1 and enilim2 are low, the chip is in its low-power shutdown state. the APW8812 only consumes 20 m a of quiescent current while in shutdown. when the enldo is higher than 2.4v and enilim1 is high (enilim1=1), the clock signal becomes available from vclk pin. both pwm outputs are discharged to 0v through a 25 w switch and both ldo outputs are dis- charged to 0v through a 40w switch in shutdown mode. driving enilim1 and enilim2 (logic and) or enldo be- low 0.4v clears the over-voltage, under-voltage and over- temperature fault latches. enable controls t h e c o n d i t i o n f o r t h e 2 7 0 k h z c l o c k s i g n a l t o b e u s e d i s t h a t t h e e n l d o i s h i g h e r t h a n 2 . 4 v a n d e n i l i m 1 i s h i g h ( e n i l i m 1 = 1 ) . w h e n v o u t 1 r e g u l a t e s a t 5 v a n d t h e c l o c k s i g n a l u s e s v o u t 1 a s i t s p o w e r s u p p l y , t h e c h a r g e p u m p c i r c u i t c a n g e n e r a t e a p p r o x i m a t e l y 1 5 v d c v o l t a g e . t h e e x a m p l e o f c h a r g e p u m p c i r c u i t i s s h o w n i n t y p i c a l a p p l i - c a t i o n c i r c u i t . c h a r g e p u m p controller turns off the low-side mosfet and triggers a constant-on-time. when the constant-on-time has expired, the controller turns on the low-side mosfet again until the inductor current is below the zero-cross- ing threshold. the behavior is the same with pfm mode.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 4 under-voltage protection (pwms) in the process of operation, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- f u n c t i o n d e s c r i p t i o n ( c o n t . ) p o k i s a c t i v e l y h e l d l o w i n s h u t d o w n , s t a n d b y , a n d s o f t - s t a r t . i n t h e s o f t - s t a r t p r o c e s s , t h e p o k i s a n o p e n - d r a i n o u t p u t , a n d i t i s r e l e a s e d w i t h e n a b l e d e l a y a f t e r t h e l a t e s t e n i l i m x g o e s h i g h ( a b o u t 2 m s t y p . ) . i n n o r m a l o p e r a t i o n , t h e p o k w i n d o w i s f r o m 9 0 % t o i t s o v p t h r e s h o l d o f t h e c o n v e r t e r r e f e r e n c e v o l t a g e . b o t h o f v o u t 1 a n d v o u t 2 h a v e t o s t a y w i t h i n t h i s w i n d o w f o r p o k t o b e h i g h ( a n d g a t e d ) . i n o r d e r t o p r e v e n t f a l s e p o k d r o p , c a p a c i t o r s n e e d t o p a r a l l e l a t t h e o u t p u t t o c o n f i n e t h e v o l t a g e d e v i a t i o n w i t h s e v e r e l o a d s t e p t r a n s i e n t . power good indicator (pwms) should the output voltage of v out1 and v out2 increase over 25% of the setting voltage due to the high-side mosfet failure or for other reasons, the over-voltage protection will active. as long as either of pwm channels triggers over-voltage, both of pwm channels active over-voltage protection. over-voltage protection will force the low-side mosfet gate driver fully turn on. this action actively pulls down the output voltage. when the ovp occurs, the pok pin will pull down and latch-off the converter. this ovp scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side mosfet driver. it?s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can be reset by toggling enldo or enilim1 and enilim2 (logic and) signal. over-voltage protection (ovp) when the junction temperature increases above the ris- ing threshold temperature 160c, the ic will enter the over-temperature protection (otp). when the otp occurs, ref, ldo and pwm controllers circuitry shuts down. it is non-latch protection. over-temperature protection in the event of pwm under-voltage or shutdown, the chip enables the soft-stop function. the soft-stop function dis- charges the pwm output voltages to gnd through an internal 25 w switch. the reference remains active to pro- vide an accurate threshold and to provide over-voltage protection. soft-stop (pwms) enilim1, enilim2 and enldo are enable signals for pwm1, pwm2 and ldos. in the single channel mode, when enilim1 or enilim2 higher than 630mv, the pwm controller enables the respective outputs, and when enilim1 or enilim2 is lower than 600mv, it disables the respective outputs. also, enilim1 and enilim2 signal timing will control pwm1 and pwm2 power-up sequence. if enilimx pin is high (enilimx=1) while other channel is starting up, its soft-start will be postponed until the other channel reaches regulation. on the other hand, if both enilim1 and enilim2 become high state at the same time (within 60 m s), both channels ramp up at the same time. about power off sequencing, both supplies begin their power-down sequence immediately when the first supply turns off. p o w e r s e q u e n c i n g ger than the value of current-limit threshold, the output voltage will fall out of the required regulation range. the under-voltage continually monitors the setting output volt- age after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under- voltage threshold for at least 2 m s, the pwm controller starts a soft-stop process to shut down the output gradually. as long as either of pwm channels triggers under-voltage, both of pwm channels active under-voltage protection and latched off when the soft-stop process is completed. the under-voltage threshold is 70% of the nominal out- put voltage. under-voltage protection is ignored for at least 2ms (typ.) after a rising edge on en. toggling enldo or enpwm signal will clear the latch and bring the chip back to operation.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) both pwm controllers use the low-side mosfets on- resistance r ds(on) to monitor the current for protection against shorted outputs. the mosfet?s r ds(on) is varied by temperature and gate to source voltage, the user should determine the maximum r ds(on) in manufacture?s datasheet. the current-limit threshold of APW8812 is adjusted with an external resistor. the enilimx pin adjustment range is from 700mv to 2v. in the adjustable mode, the current- limit threshold voltage is 1/10 th the voltage at enilimx pin. as shown in figure 2, the enilimx pin can source 10 m a. the voltage at enilimx pin is equal to 10 m a x r ilim . con- nect ilim to ref for a fixed 200mv threshold. the logic current-limit threshold is default to 250mv value if enilimx is 5v. the relationship between the sampled voltage v ilim and the current-limit threshold i limit is given by: where v enilimx is the voltage at the enilimx pin. r ds(on) is the low side mosfets conducive resistance. i limit is the setting current-limit threshold. i limit can be expressed as i out minus half of peak-to-peak inductor current. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. ) on ( ds limit enilimx r i v 10 1 = figure 2. current-limit setting block diagram the current-limit circuit employs a ?valley? current-sens- ing algorithm (see figure 1). the APW8812 uses the low-side mosfet?s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at phase pin is above the current- limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current- limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage. current-limit (pwms) figure 1. current-limit algorithm time i n d u c t o r c u r r e n t 0 i peak i out i limit d i vcc 10 m a to current limit logic 9r r enilim v eni lim r ilim
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) table 1. operating mode truth table mode condition comment run enldo = 1, enilimx =1 pwm is in normal operation. standby & soft - stop enpwm=0, enldo=1 if pwmx is in shutdown, discharge switch (25 w ) connects their voutx to gnd . ldox and ref active. shutdown en pwm=0 and en ldo=0 pwmx outpu t discharge switch (25 w ) connects voutx to gnd. ldox discharge switch (40 w ) connects ldox to gnd. in this mode, all circuitry is off. uvp either v out1 , or v out2 < 70% of nominal output voltage the internal 25 w switch turns on to pull low output voltage. ldox and ref are active. r eset by toggling en ilim1 and enilim2 (logic and) or en ldo single. ovp either v out1 and v out2 > 125% of normal output voltage lgate of two pwm channel are forced high. ldox and ref active. r eset by toggling en ilim1 and enilim2 ( logic and) or enldo single. otp t j > +160 o c all circuitry off. it is non - latch protection after the junction temperature cools by 25 o c. table 2. power-up control logics v enldo v enilim1 v enilim2 ldo5 ldo3 pwm1 pwm2 vclk low don ? t care don ? t care off off off off off 0.8v ~ 1.6v low low on on off off off 0.8v ~ 1.6v high high on on on on off 0.8v ~ 1.6v high low on on on off off 0.8v ~ 1.6v low high on on off on off 0. 8v ~ 1.6v high high (after enilim1 is high without 60 m s) on on on on (after pwm1 is pok) off 0.8v ~ 1.6v high (after enilim2 is high without 60 m s) high on on on (after pwm2 is pok) on off > 2.4v low low on on off off off > 2.4v high high on on on on on > 2.4v high low on on on off on > 2.4v low high on on off on off > 2.4v high high(after enilim1 is high without 60 m s) on on on on (after pwm1 is pok) on > 2.4v high(after enilim2 is high without 60 m s) high on on on (after pwm2 is pok) on on
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n the output voltage of pwm1 can be adjusted from 2v to 5.5v with a resistor-driver at fb1 between vout1 and gnd. using 1% or better resistors for the resistive di- vider is recommended. the fb1 pin is the inverter input of the error amplifier, and the reference voltage is 2v. take the example, the output voltage of pwm1 is deter- mined by: w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . i n c r e a s i n g t h e i n d u c t o r v a l u e a n d f r e q u e n c y w i l l r e - d u c e t h e r i p p l e c u r r e n t a n d v o l t a g e . h o w e v e r , t h e r e i s a t r a d e o f f b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a s m a l l e r i n d u c t o r w i l l g i v e t h e r e g u l a t o r a f a s t e r l o a d t r a n s i e n t r e s p o n s e a t t h e e x p e n s e o f h i g h e r r i p p l e c u r r e n t . i n c r e a s i n g t h e s w i t c h i n g f r e q u e n c y ( f s w ) a l s o r e d u c e s t h e r i p p l e c u r r e n t a n d v o l t a g e , b u t i t w i l l i n c r e a s e t h e s w i t c h i n g l o s s o f t h e m o s f e t s a n d t h e p o w e r d i s s i p a t i o n o f t h e c o n v e r t e r . t h e m a x i m u m where r top 1 is the resistor connected from v out i to v fb1 and r gnd 1 is the resistor connected from fb1 to gnd. similarly, the output voltage of pwm2 can be alsoadjusted from 2v to 5.5v. o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value determines the inductor ripple current and affects the load transient reponse. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current can be approxminated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d these two components constitute a large portion of the total output voltage ripple . in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support an other load with high pulsating current, more capaci- tors are needed in order to reduce th e equivalent esr and s uppress the voltage ripple to a tolerable level. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors must also be considered. to support a load transient that is faster than the switching frequency, more capacitors have to be used to reduce the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac current going through the capaci tors has to be less than the rated rms current specified on the ca- pacitors to prevent the capacitor from over-heating. ? ? ? ? ? + = gnd1 top1 outi r r 1 2 v r i p p l e c u r r e n t o c c u r s a t t h e m a x i m u m i n p u t v o l t a g e . a g o o d s t a r t i n g p o i n t i s t o c h o o s e t h e r i p p l e c u r r e n t t o b e a p p r o x i m a t e l y 3 0 % o f t h e m a x i m u m o u t p u t c u r r e n t . o n c e t h e i n d u c t a n c e v a l u e h a s b e e n c h o s e n , s e l e c t i n g a n i n d u c t o r i s c a p a b l e o f c a r r y i n g t h e r e q u i r e d p e a k c u r - r e n t w i t h o u t g o i n g i n t o s a t u r a t i o n . i n s o m e t y p e s o f i n d u c t o r s , e s p e c i a l l y c o r e t h a t i s m a d e o f f e r r i t e , t h e r i p p l e c u r r e n t w i l l i n c r e a s e a b r u p t l y w h e n i t s a t u r a t e s . t h i s w i l l b e r e s u l t i n a l a r g e r o u t p u t r i p p l e v o l t a g e . o u t p u t v o l t a g e s e l e c t i o n o u t p u t v o l t a g e r i p p l e a n d t h e t r a n s i e n t v o l t a g e d e - v i a t i o n a r e f a c t o r s t h a t h a v e t o b e t a k e n i n t o c o n s i d - e r a t i o n w h e n s e l e c t i n g a n o u t p u t c a p a c i t o r . h i g h e r c a p a c i t o r v a l u e a n d l o w e r e s r r e d u c e t h e o u t p u t r i p p l e a n d t h e l o a d t r a n s i e n t d r o p . t h e r e f o r e , s e l e c t i n g h i g h p e r f o r m a n c e l o w e s r c a p a c i t o r s i s i n t e n d e d f o r s w i t c h - i n g r e g u l a t o r a p p l i c a t i o n s . i n a d d i t i o n t o h i g h f r e q u e n c y n o i s e r e l a t e d m o s f e t t u r n - o n a n d t u r n - o f f , t h e o u t p u t v o l t a g e r i p p l e i n c l u d e s t h e c a p a c i t a n c e v o l t a g e d r o p a n d e s r v o l t a g e d r o p c a u s e d b y t h e a c p e a k - t o - p e a k c u r r e n t . t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 8 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r u p , t h e i n p u t c a p a c i - t o r s h a v e t o h a n d l e l a r g e a m o u n t o f s u r g e c u r r e n t . i n l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r s a r e r e m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . m o s f e t s e l e c t i o n t h e a p p l i c a t i o n f o r a n o t e b o o k b a t t e r y w i t h a m a x i m u m v o l t - a g e o f 2 4 v , a t l e a s t a m i n i m u m 3 0 v m o s f e t s s h o u l d b e u s e d . t h e d e s i g n h a s t o t r a d e o f f t h e g a t e c h a r g e w i t h t h e r ds(on) o f t h e m o s f e t : f o r t h e l o w - s i d e m o s f e t , b e f o r e i t i s t u r n e d o n , t h e b o d y d i o d e h a s b e e n c o n d u c t e d . t h e l o w - s i d e m o s f e t d r i v e r w i l l n o t c h a r g e t h e m i l l e r c a p a c i t o r o f t h i s m o s f e t . i n t h e t u r n i n g o f f p r o c e s s o f t h e l o w - s i d e m o s f e t , t h e l o a d c u r r e n t w i l l s h i f t t o t h e b o d y d i o d e f i r s t . t h e h i g h d v / d t o f t h e p h a s e n o d e v o l t a g e w i l l c h a r g e t h e m i l l e r c a p a c i t o r t h r o u g h t h e l o w - s i d e m o s f e t d r i v e r s i n k i n g c u r r e n t p a t h . t h i s r e s u l t s i n m u c h l e s s s w i t c h i n g l o s s o f t h e l o w - s i d e m o s f e t s . t h e d u t y c y c l e i s o f t e n v e r y s m a l l i n h i g h b a t t e r y v o l t a g e a p p l i c a t i o n s , a n d t h e l o w - s i d e m o s f e t w i l l c o n - d u c t m o s t o f t h e s w i t c h i n g c y c l e ; t h e r e f o r e , t h e l e s s t h e r ds(on) o f t h e l o w - s i d e m o s f e t , t h e l e s s t h e p o w e r l o s s . t h e g a t e c h a r g e f o r t h i s m o s f e t i s u s u a l l y a s e c o n d a r y c o n s i d e r a t i o n . t h e h i g h - s i d e m o s f e t d o e s n o t h a v e t h i s z e r o v o l t a g e s w i t c h i n g c o n d i t i o n , a n d b e c a u s e i t c o n d u c t s f o r l e s s t i m e c o m p a r e d t o t h e l o w - s i d e m o s f e t , t h e s w i t c h i n g l o s s t e n d s t o b e d o m i n a n t . p r i o r i t y s h o u l d b e g i v e n t o t h e m o s f e t s w i t h l e s s g a t e c h a r g e , s o t h a t b o t h t h e g a t e d r i v e r l o s s a n d s w i t c h i n g l o s s w i l l b e m i n i m i z e d . p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet include s an additional transi - tion loss. t he switching internal, t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs temperature? curve of the power mosfet. l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w e r m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . a n d s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a r a t i n g a n d f i n a l l y c o m b i n e d t o u s e t h e g r o u n d p l a n e c o n s t r u c t i o n o r s i n g l e p o i n t g r o u n d i n g . t h e b e s t t i e - p o i n t b e t w e e n t h e s i g n a l g r o u n d a n d t h e p o w e r g r o u n d i s a t t h e n e g a t i v e s i d e o f t h e o u t p u t c a p a c i t o r o n e a c h c h a n n e l , w h e r e t h e r e i s l e s s n o i s e . n o i s y t r a c e s b e n e a t h t h e i c a r e n o t r e c o m m e n d e d . b e l o w i s a c h e c k l i s t f o r y o u r l a y o u t : t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e - t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c - t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 1 9 l a y o u t c o n s i d e r a t i o n ( c o n t . ) a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) k e e p t h e s w i t c h i n g n o d e s ( u g a t e x , l g a t e x , b o o t x , a n d p h a s e x ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s ( r e f , i l i m x , a n d f b x ) s i n c e t h e s e n o d e s a r e f a s t m o v - i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t , w i t h h i g h p e a k c h a r g i n g a n d d i s c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e x a n d l g a t e x ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e - t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . d e c o u p l i n g c a p a c i t o r , t h e r e s i s t o r d i v i d e r s , b o o t c a p a c i t o r s , a n d c u r r e n t - l i m i t s t e t t i n g r e s i s t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r n e a r t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . t h e b u l k c a p a c i t o r s a r e a l s o p l a c e d n e a r t h e d r a i n ) . t h e i n p u t c a p a c i t o r s h o u l d b e n e a r t h e d r a i n o f t h e u p p e r m o s f e t ; t h e h i g h q u a l i t y c e r a m i c d e c o u p l i n g c a p a c i t o r c a n b e p u t c l o s e t o t h e v c c a n d g n d p i n s ; t h e o u t p u t c a p a c i t o r s h o u l d b e n e a r t h e l o a d s . t h e i n p u t c a p a c i t o r g n d s h o u l d b e c l o s e t o t h e o u t p u t c a - p a c i t o r g n d a n d t h e l o w e r m o s f e t g n d . t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e x n o d e s ) s h o u l d b e a l a r g e p l a n e f o r h e a t s i n k i n g . a n d p h a s e x p i n t r a c e s a r e a l s o t h e r e t u r n p a t h f o r u g a t e x . c o n - n e c t t h e s e p i n s t o t h e r e s p e c t i v e c o n v e r t e r ? s u p p e r m o s f e t s o u r c e . t h e c o n t r o l l e r u s e d r i p p l e m o d e c o n t r o l . b u i l d t h e r e - s i s t o r d i v i d e r c l o s e t o t h e f b 1 p i n s o t h a t t h e h i g h i m p e d a n c e t r a c e i s s h o r t e r w h e n t h e o u t p u t v o l t a g e i s i n a d j u s t a b l e m o d e . a n d t h e f b 1 p i n t r a c e s c a n ? t b e c l o s e t o t h e s w i t c h i n g s i g n a l t r a c e s ( u g a t e x , l g a t e x , b o o t x , a n d p h a s e x ) . t h e p g n d t r a c e s h o u l d b e a s e p a r a t e t r a c e , a n d i n - d e p e n d e n t l y g o t o t h e s o u r c e o f t h e l o w - s i d e m o s f e t s f o r c u r r e n t - l i m i t a c c u r a c y . t q f n 4 x 4 - 2 4 a 0 . 5 mm 0 . 25 mm 0 . 46 mm 4 mm * just recommend 0 . 5 mm * 4 mm 2 . 2 5 m m 2 . 25 mm 0 . 4 mm thermalvia diameter 0 . 3 mm x 4
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 0 p a c k a g e i n f o r m a t i o n t q f n 4 x 4 - 2 4 a pin 1 d e pin 1 corner d 2 e 2 k l e s y m b o l min . max . 0 . 80 0 . 00 0 . 18 0 . 30 2 . 00 2 . 50 0 . 05 2 . 00 a a 1 b d d 2 e e 2 e l millimeters a 3 0 . 20 ref tqfn 4 x 4 - 24 a 0 . 35 0 . 45 2 . 50 0 . 008 ref min . max . inches 0 . 032 0 . 000 0 . 007 0 . 012 0 . 079 0 . 098 0 . 079 0 . 014 0 . 018 0 . 70 0 . 098 0 . 028 0 . 002 0 . 50 bsc 0 . 020 bsc k 0 . 20 0 . 008 3 . 90 4 . 10 0 . 154 0 . 161 3 . 90 4 . 10 0 . 154 0 . 161 a b a 1 a 3 nx c aaa aaa 0 . 08 0 . 003
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 1 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfn4x4 - 24a 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 4.30 ? 0.20 4.30 ? 0.20 1.25 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity tqfn4x4 - 24a tape & reel 3000 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 2 t a p i n g d i r e c t i o n i n f o r m a t i o n tqfn4x4-24a c l a s s i f i c a t i o n p r o f i l e supplier t p ? t c supplier t p user t p ?? t c user t p t t s time t e m p e r a t u r e t p t l t p t c -5 o c 25 time 25 o c to peak max. ramp up rate = 3 o c/s max. ramp down rate = 6 o c/s preheat area t smax t smin t c t c -5 o c user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 3 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n r e f l o w p r o f i l e s table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 2 - s e p . , 2 0 1 2 a p w 8 8 1 2 w w w . a n p e c . c o m . t w 2 4 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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